Current mode sense amplifiers in memory devices are sensitive to voltage changes on data lines, such as those lines commonly referred to as bit lines of the memory. Due to adjacent bit line noise coupling, noise on the bit lines can cause a sense amplifier to trip falsely, leading to corrupted data at the sense amplifier output. In other words, if there is noise on the bit line, the sense amplifier could trigger even though a valid signal is not present. This can happen due to the way that threshold voltages are typically set in a NAND memory. In typical NAND memories, when a current of 100 nanoAmperes (nA) flows through a selected cell in the NAND string, the voltage when the current reaches that 100 nA is set as the threshold voltage of the cells. Noise on a bit line due to neighboring bit lines can exceed the sense amplifier (SA) noise margin and cause false signals at the sense amplifier output.
A typical NAND circuit is shown in FIG. 1. The core of the circuit comprises transistors MNSRC 102 and MNBL 104, which are biased by transistors MPB1 106 and MPB2 107. A RESET pulse is used in a reset phase to pre-charge the bit line 110 and to reset the sense amplifier output 112 to low, as is known. Node N2 is charged to Vcc, and sense amplifier output 112 is set to low.
In a read/sense phase, after the selected NAND string 114 is turned on, the bit line 110 starts to discharge, and transistor MNSRC 102 turns off. The voltage at node N1 rises, and transistor MNBL 104 turns on, discharging node N2 from Vcc and flipping sense amplifier output 112 from low to high as transistor MPIV 116 turns on.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improvements in noise tolerance in NAND memories.